Studies on Hierarchical Two-Pattern Testability of Controller-Data Path Circuits

Two-pattern test is required to identify delay faults in a circuit. The importance of delay fault testing is increasing gradually because of the fact that traditional stuck-at fault testing is failing to guarantee an acceptable quality level for today’s high-speed chips. Some defects and/or random process variation do not change the steady state behavior of a circuit but affect the at speed performance. Any degradation in at speed performance is detected by delay testing and it is likely to become industrially accepted in near future. A straightforward solution to two-pattern testability is the enhanced-scan design. But this incorporates very high area overhead and long test application time. In this thesis we present a hierarchical testability technique for delay faults. There are a number of delay fault models. Among these, the path delay fault model is more general and can overcome the limitations of other models. Our approach is developed on path delay fault model. The design hierarchy we consider is (Register Transfer Level) RTL, where the number of primitive elements in the circuit is greatly reduced. At RTL a circuit can be divided into two parts: a controller and a data path. Firstly, we consider the data path as a separate entity. We introduce the concept of RTL paths in a data path. Based on this we develop the definition of hierarchically twopattern testable (HTPT) data path. The advantages of an HTPT data path are (i) the data path can be tested using any delay fault model, (ii) combinational (Automatic Test Pattern Generation) ATPG can be used and (iii) the same fault coverage can be obtained as with the enhanced scan approach. We also point out some necessary and sufficient conditions to support the propagation of two-pattern vectors via two or more control paths in a data path.